Semiconductor apparatus

ABSTRACT

A semiconductor apparatus of the present invention comprises, as, for example, shown in FIG. 5, a semiconductor region (32) of first conductivity type formed on a semiconductor substrate (31), and a semiconductor region (34) of second conductivity type formed in the semiconductor region (32) of first conductivity type, in which a first electrode (38a) is formed on the semiconductor region (34) of second conductivity type to form a capacitance through a dielectric layer (37), a second electrode (38c) connected to the semiconductor region (32) of first conductivity type is provided and a third electrode (38b) connected to the semiconductor region (34) of second conductivity type is provided, whereby easiness (capacitor) can be prevented from being affected by a junction capacitance between semiconductor layers of different conductivity types.

This is a continuation of application Ser. No. 423,425, filed Sep. 22,1989, now abandoned.

TECHNICAL FIELD

The present invention relates to a semiconductor apparatus which caneliminate an influence exerted by a parasitic capacitance, and which canalleviate restrictions on the driving condition.

BACKGROUND ART

In a prior-art home VTR, in a recording system and a reproducing systemthere is commonly provided a so-called ACC circuit in which an amplitudeof a color burst signal is detected to control a gain of a chrominancesignal amplifier thereby maintaining an amplitude of the chrominancesignal constant FIG. 4 shows a previously-proposed semiconductorapparatus used in this ACC circuit.

The VTR and the ACC circuit according to the prior art will be describedwith reference to FIGS. 1 and 2.

FIG. 1 shows an example of an arrangement of a reproducing system of aprior-art VTR.

Referring to FIG. 1, reproduced outputs from a pair of rotary magneticheads 1A and 1B are commonly supplied through a head change-over switch2 and an amplifier 3 to a high-pass filter 4 and a low-pass filter 5from which there are separated an FM luminance signal Y_(FM) and a downconverted chrominance signal C_(L).

The FM luminance signal Y_(FM) is supplied to a luminance signalprocessing circuit 7 which includes an FM-demodulator 6, and areproduced luminance signal Y therefrom is supplied to an adder 8.

The down-converted chrominance signal C_(L) is supplied through achrominance signal amplifier 11 to a frequency converting circuit 12, inwhich it is converted to an original carrier chrominance signal C inresponse to an output from a local oscillator not shown The reproducedcarrier chrominance signal C from the frequency converting circuit 12 issupplied to the adder 8 through a bandpass filter 13 whose centerfrequency is a color subcarrier frequency fsc, and the adder 8 derives acolor video signal

A burst gate circuit 14 is supplied with the output of the bandpassfilter 13, and the reproduced color burst signal extracted thereby issupplied to an ACC detector 15. The detected output therefrom issupplied through an ACC circuit 20 to the chrominance signal amplifier11 of which the gain is therefore ACC-controlled.

In order to protect the chrominance signal from a flicker caused by anoutput level difference when the characteristics of the rotary magneticheads 1A and 1B are not equal, the ACC circuit 20 employs capacitors 21Aand 21B of the same capacitance to form time constant circuits havingtime constants different in field. The time constant circuits arechanged-over by the switching pulse from a pulse generator 9 insynchronism with the switching operation of the rotary heads 1A and 1B.

As shown in FIG. 2, in the prior-art ACC circuit 20, the capacitors 21Aand 21B are respectively connected to output terminals of differentialamplifiers (comparing circuits) 22A and 22B. The differential amplifiers22A and 22B are alternately supplied at non-inverting input terminalsthereof with a detected output V₁₅ applied to an input terminal 20i ofthe ACC circuit 20 from the ACC detector 15 through a change-over switch23i at every field, and they are also commonly supplied at theirinverting input terminals with a reference voltage Vr of a referencevoltage source 24. The differential amplifiers 22A and 22B respectivelysupply the corresponding capacitors 21A and 21B with output currentscorresponding to differences between the ACC detected output voltage V₁₅and the reference voltage Vr. The terminal voltages across thecapacitors 21A and 21B are alternately supplied through bufferamplifiers (buffers) 25A and 25B and a change-over switch 23o to anoutput terminal 20o at every field. The switches 23i and 23o are changedin position at every field in response to the switching pulse from acontrol terminal 20c in a ganged-fashion.

In the conventional ACC circuit shown in FIG. 2, the two signal systemsrespectively including the differential amplifiers 22A and 22B areswitched by the switches 23i and 23o, which provides a large-sizedcircuit scale and a complicated arrangement. Further, even when they areformed as an integrated circuit on the same semiconductor substrate,there is then a fear that an offset will occur between thecharacteristics of the two differential amplifiers.

To solve the above-noted problem, the present applicant has previouslyproposed, as disclosed in Japanese Utility Model Application No.61-200570, an Acc circuit in which an output of a single comparingcircuit is held by a plurality of capacitors which are switched at everyfield in synchronism with the change-over of rotary heads.

The previously-proposed ACC circuit will be explained with reference toFIG. 3.

FIG. 3 shows an example of an arrangement of the previously-proposed ACCcircuit. In FIG. 3, like parts corresponding to those of FIG. 2 aremarked with the same references.

In FIG. 3, reference numeral 20S generally designates an ACC circuitwhich mainly comprises a single differential amplifier 22, a pair ofcapacitors 21A and 21B whose one electrodes are commonly connected tothe output terminal of the differential amplifier and a change-overswitch 26 which alternately grounds the other electrodes of the twocapacitors 21A and 21B at every field.

The previously-proposed ACC circuit 20S is operated as follows.

When one rotary head 1A (see FIG. 1) scans a magnetic tape, thechange-over switch 26 is connected as shown by a dashed line. The ACCdetected output from the input terminal 20i and the reference voltage Vrare level-compared by the differential amplifier 22, and a currentcorresponding to the level difference is supplied from the differentialamplifier 22 to one capacitor 21A. Thus, its terminal voltage becomes avalue corresponding to the difference between the burst signal level andthe reference voltage Vr.

When the other rotary head 1B scans the magnetic tape, the switch 26 isconnected as shown by a solid line, whereby the other capacitor 21B ischarged up similarly as described above.

The terminal voltages across the capacitors 21A and 21B are deliveredthrough, for example, an emitter-follower-type buffer 25 to the outputterminal 20o and then supplied to the amplifier 11 (see FIG. 1). Thegain of the amplifier 11 is therefore controlled such that the level ofthe color burst signal coincides with the reference level

According to the previously-proposed ACC circuit as described above,only the single differential amplifier is required so that the circuitscale becomes small, the arrangement is simplified and that the offsetis prevented from being caused between the differential amplifiers.

When the above-mentioned, previously-proposed ACC circuit is formed on asemiconductor circuit (formed as an IC) including the capacitors 21A and21B, it is unavoidable that the capacitors 21A and 21B are accompaniedwith parasitic capacitances 27A and 27B a shown by dashed lines in FIG.3.

This is because the capacitor mounted on the semiconductor integratedcircuit is generally formed as a so-called MIS (metal insulationsubstrate) capacitance as shown in FIG. 4.

In FIG. 4, reference numeral 31 designates a P-type silicon substrate inwhich an N-type epitaxial layer 32 is formed on its surface portion asan island-shape. Further, an n⁺ -type diffusion layer 33 is selectivelyformed on the surface portion of the N-type epitaxial layer 32 by theemitter diffusion-process. Through an oxide film 35 for protecting thesurface of the semiconductor, large and small windows 36a nd 36b areformed on the diffusion layer 33.

A dielectric layer 37 is, for example, 500 Å in thickness and is made ofnitride silicon Si₃ N₄. This dielectric layer is deposited on the n⁺-type diffusion layer 33 within the large window 36a of the oxide film35. An Al electrode 38a is deposited on the dielectric layer 37 and anAl electrode 38b is deposited on the diffusion layer 33 within the smallwindow 36b, whereby the diffusion layer 33 and the Al electrode 38a areopposed to each other through the dielectric layer 37, thus forming acapacitor having a capacitance of, for example, 100 pF.

A junction capacitance C_(j) exists between the n-type island 32communicated to the n⁺ -type diffusion layer 33 and the p-type siliconsubstrate 31 of earth potential as is conventional, and this junctioncapacitance C_(j) becomes the parasitic capacitance of the capacitorwhich is constructed by the MIS technique. The value of the parasiticcapacitance depends on constituents of the p-type silicon substrate 31and the n-type island 32, and is generally about 10% of the capacitanceof the capacitor constructed by the MIS technique.

The p-type substrate 31 and the n-type island 32 have a characteristicof a diode D_(j) as well as the above-noted junction capacitance C_(j).

If the previously-proposed ACC circuit shown in FIG. 3 is formed as anIC, the parasitic capacitances 27A and 27B are produced by theabove-noted junction capacitance so that the independence of the twocapacitors 21A and 21B will no be kept even if the switch 26 is changedover.

When the change-over switch 26 is connected as shown by the solid linein FIG. 3, to the other capacitor 21B grounded thereby, a serially-mixedcapacitance of one capacitor 21A and the parasitic capacitance 27Athereof is connected in parallel.

In like a manner, when the switch 26 is connected as shown by the dashedline, to one capacitor 21A, a serially-mixed capacitance of the othercapacitor 21B and the parasitic capacitance 27B thereby is connected in

Assuming that the capacitance values of the parasitic capacitances 27Aand 27B are, for example, 10% of the capacitance values of thecorresponding capacitors 21A and 21B respectively as describedhereinabove, then the values of the serially-mixed capacitances reach,for example, values a little larger than 9 % of the capacitance valuesof the capacitors 21A and 21B.

Thus, when the previously-proposed ACC circuit 20S is formed as an IC,the independence of each of the capacitors 21A and 21B is damaged sothat a cross-talk occurs between the ACC control signals of each fieldheld in the capacitors 21A and 21B. As a result, the flicker of thechrominance signal can not be eliminated completely.

If the output current from the differential amplifier 22 is suppliedthrough the change-over switch to first electrodes of the pair ofcapacitors and the second electrodes of the two capacitors are groundedunlike FIG. 3, the problem of the parasitic capacitances will be solved.There are then presented problems such as the occurrence of a leakcurrent of a switching element used to switch the current, a decrease ofD.C. voltage availability (dynamic range) and the like.

In the semiconductor apparatus of FIG. 4, the dielectric layer 37 isthin in thickness and is small in electrostatic strength, whereby theelectrode 38a is interconnected and the electrode 38b is led out to theoutside as an MIS capacitance terminal. When the potential of theelectrode 38b is lowered to the winding region, the junction diode Dj isturned ON, permitting an excess current to flow from the substrate 31 tothe n-type island 32. There is then presented a problem that it becomesimpossible to use the semiconductor apparatus.

DISCLOSURE OF INVENTION

In view of the above-mentioned aspect, an object of the presentinvention is to provide a semiconductor apparatus which can reducerestrictions on driving conditions, and which can eliminate an influenceof parasitic capacitance exerted on an MIS capacitance.

A semiconductor apparatus of the present invention comprises asemiconductor region 32 of a second conductivity type formed on asemiconductor substrate 31 of a first conductivity type and asemiconductor area 34 of a first conductivity type formed in thesemiconductor region of the second conductivity type, wherein a first Alelectrode 38a is formed on the semiconductor area of the firstconductivity type through a dielectric layer 37 to form a capacitanceand first and second deriving electrodes 38b and 38c are formed on thesemiconductor regions of the first and second conductivity types.

In a semiconductor apparatus of the present invention, a semiconductorregion 34 of first conductivity type is formed on a semiconductorsubstrate 31 of first conductivity type through a semiconductor region32 of second conductivity type, a conductive layer 38a is opposedthrough a dielectric layer 37 to the semiconductor layer of firstconductivity type to form a capacitor 21, one of electrodes ○A and ○B ofthis capacitor is connected to an input terminal of a buffer amplifier25 mounted on the semiconductor substrate, and an output terminal of thebuffer amplifier and a deriving electrode ○C led out from thesemiconductor region of second conductivity type are connected.According to the present invention as described above, the capacitor 21Aor 21B formed according to the MIS technique is floated so that it canbe prevented from being affected by a Junction capacitance between thesemiconductor layers of different conductivity types. Further, thepotential of the deriving electrode is expanded in range.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 and 2 are a block diagram and a connection diagram to whichreference will be made in explaining the present invention,

FIG. 3 is a connection diagram showing an example of an arrangement of apreviously-proposed ACC circuit,

FIG. 4 is a diagrammatic view of a section showing an arrangement of anexample according to the prior art,

FIG. 5 is a diagrammatic view of a section showing an arrangement of anembodiment of a semiconductor apparatus according to the presentinvention,

FIGS. 6 and 7 are connection diagrams showing arrangements of otherembodiments in which the present invention is applied to the ACCcircuit, respectively and

FIG. 8 is a diagrammatic view of a section showing an arrangement of afurther embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of a semiconductor apparatus according to the presentinvention will hereinafter be described with reference to FIG. 5.

FIG. 5 shows an arrangement of an embodiment of the present invention.In FIG. 5, like parts corresponding to those of FIG. 4 are marked withthe same references and therefore an overlapping explanation will not bemade.

As shown in FIG. 5, a p-type diffusion layer 34 is selectively formed onthe surface portion of the island-shaped n-type epitaxial layer 32 by abase-diffusion process. The large window 36a and the small window 36bare formed through the protecting film 35 on the p-type diffusion layer34, and a second small window 36c is formed through the protecting film35 on the surface of the n-type island 32. Within this small window 36c,an Al electrode 38c is deposited on the n-type island 32.

Similarly as described hereinbefore, a junction capacitance C_(i) and adiode D_(j1) are formed between the p-type substrate 31 and the n-typeisland 32, and a junction capacitance C_(j2) and a diode D_(j2) areformed between the n-type island 32 and the p-type diffusion layer 34.Other arrangements are similar to those of FIG. 4.

With the above-mentioned arrangement, if a negative potential issupplied to the p-type diffusion layer 34 through the Al electrode 38b,then the diode D_(j2) formed between the p-type diffusion layer and then-type island 32 is reversely biased to prevent the potential of then-type island 32 from being lowered to the negative region. Thus, thediode D_(jl) formed between the island 32 and the p-type substrate 31 isturned ON, thus avoiding the excess current from flowing.

As described above, according to this embodiment, the negative potentialmay be supplied to the p-type diffusion layer 34 and a range ofavailable voltage can be extended compared with the example according tothe prior art.

How to eliminate the influence by the junction capacitance will beexplained below.

A semiconductor apparatus according to other embodiment, which isapplied to an ACC circuit of a VTR, will be described next withreference to FIG. 6.

FIG. 6 shows an arrangement of another embodiment of the presentinvention which is applied to the ACC circuit. In FIG. 6, like partscorresponding to those of FIG. 3 are marked with the same references andan overlapping explanation will therefore not be made.

In FIG. 6, reference numeral 20F generally designates an ACC circuit, inwhich third and fourth parasitic capacitances 28A and 28B arerespectively connected in series between the capacitors 21A, 21B and thecorresponding parasitic capacitances 27A, 27B. A junction ○B between onecapacitor 21A and the parasitic capacitance 28A is connected to onefixed contact of the switch 26, while a junction between the othercapacitor 21B and the parasitic capacitance 28B is connected to theother fixed contact of the switch 26. A junction ○C between the firstand third parasitic capacitances 27A and 28A and a junction between thesecond and fourth parasitic capacitances 27B and 28B are both connectedto an intermediate terminal Q, and this terminal Q and the outputterminal of the buffer 25 are connected to each other.

The third and fourth parasitic capacitances 28A and 28B are formed asshown in FIG. 5. The terminal ○A of the capacitor 21A and the junctions○B and ○ correspond to the A(electrodes 38a, 38b and 38c of FIG. 5,respectively. Other arrangements are similar to those of FIG. 3.

The operation of the embodiment of FIG. 6 is as follows.

When the change-over switch 26 is connected as, for example, shown by asolid line, the other capacitor 21B is directly grounded. One capacitor21A is grounded via the first and third parasitic capacitances 27A and28A. In this embodiment, the output terminal of the buffer 25 isconnected through the intermediate terminal Q to the junction ○C of thetwo parasitic capacitances 27A and 28A so that the first parasiticcapacitance 27A is connected in parallel to the low output impedance ofthe buffer 25, thus the first parasitic capacitance being substantiallyshort-circuited.

Further, since the potential at the output terminal of the buffer 25 ischanged in the same way as the potential at the input terminal thereofis changed, a potential difference between the input and outputterminals of the buffer 25 becomes constant. In this embodiment, forexample, one capacitor 21A and the third parasitic capacitance 28A areserially connected between the input and output terminals of the buffer25 so that, even if they are connected to the output terminal of thedifferential amplifier 22, the voltage across the serially-mixedcapacitance becomes constant.

In the example of the previously-proposed semiconductor apparatus shownin FIG. 3, since the voltage across the serially mixed capacitances of,for example, one capacitor 21A and the parasitic capacitance 27A ischanged together with the voltage across the other capacitor 21B, theindependence of the two capacitors 21A and 21B is not damaged.

In the embodiment shown in FIG. 6, however, the voltage across theserially-mixed capacitance of, for example, one capacitor 21A and thethird parasitic capacitance 28A becomes constant as described above sothat the independence of the two capacitors 21A and 21B is not damaged.Thus, a cross-talk component can be prevented from being producedbetween the ACC control signals of every field, and hence, a flicker ofthe chrominance signal can be eliminated completely.

A semiconductor apparatus according to a further embodiment of thepresent invention, which is applied to the ACC circuit of a VTR, will beexplained next with reference to FIG. 7.

In FIG. 7, like parts corresponding to those of FIGS. 6 and 3 are markedwith the same references and an overlapping explanation will not bemade.

In FIG. 7, reference numeral 20H represents generally an ACC circuit, inwhich similarly to the embodiment of FIG. 6, the third and fourthparasitic capacitances 28A and 28B are serially connected between thecapacitors 21A, 21B and the corresponding parasitic capacitances 27A,27B, respectively. In this embodiment, however, the connections of theterminals of the capacitors 21A and 21B are inverted.

That is, one electrodes ( ○A ) of the capacitors 21A and 21B arerespectively connected to the fixed contacts of the change-over switch26, and the junction ○B between one capacitor 21A and the parasiticcapacitance 28A and the junction between the other capacitor 21B and theparasitic capacitance 28B are both connected to the output terminal ofthe differential amplifier 22. As described hereinbefore, the parasiticcapacitances, for example, 27A and 28A correspond to the junctioncapacitances C_(jl) and C_(j2) of FIG. 5, and which are accompanied withleak currents on the respective junction surfaces of the p-typesubstrate 31, the n-type island 32 and the p-type diffusion layer 34.Reference numeral 29 designates a leak resistor corresponding to theleak currents of the parasitic capacitances 27A, 28A and 27B, 28B. Otherarrangements are similar to those of FIG. 6.

In the embodiment of FIG. 7, the leak resistor 29 is connected to theoutput terminal of the low impedance of the differential amplifier 22,so that the leak current corresponding to the leak resistor is cancelledout by the output current of the amplifier 22.

Since one terminal ○A of the capacitor 21A, or electrode 38a isinsulated from the p-type diffusion layer 34 by the dielectric layer 37,the leak current is very small, and the influence of leak current in theholding period is also very small.

When the current is negatively fed back from the buffer 25 to thedifferential amplifier 22, the influence of the leak current can besubstantially neglected.

While in the above-mentioned embodiment the present invention is appliedto the ACC circuit of the VTR, the present invention is not limited tothe above-noted embodiment and can be made suitable for a wide varietyof circuits such as a time-division hold circuit or the like.

A further embodiment of the semiconductor apparatus according to thepresent invention will be described with reference to FIG. 8.

In FIG. 8, like parts corresponding to those of FIGS. 4 and 5 are markedwith the same references and an overlapping explanation will not bemade.

In FIG. 8, reference numeral 39 designates an n⁺ -type diffusion layerof low resistance value which is selectively formed on the surfaceportion of the p-type diffusion layer 34 by the emitter-diffusionprocess. The location of the n⁺ -type diffusion layer 39 is determinedsuch that its one border with the p-type diffusion layer 34 in thelateral direction (face direction) is opposed to the small window 36b ofthe protecting film 35. Other arrangements are similar to those of FIG.5.

In the arrangement of FIG. 8, the n⁺ -type diffusion layer 39 iscontacted with the dielectric layer 37 to form the other electrode andthe lead wire of the capacitor by the MIS technique together with thep-type diffusion layer 34. Since the diffusion layer 39 is low inresistance value as described above, the deriving resistance of the MIScapacitor is reduced, the capacitor is reduced in loss and the frequencycharacteristic can be improved.

Base and emitter of an npn-system transistor TR formed by the n-typeisland 32, the p-type diffusion layer 34 and the n⁺ -type diffusionlayer 39 are short-circuited by the Al electrode 38b.

Thus, even when the negative potential is supplied to the n-type island32 through the Al electrode 38b, the transistor TR is in its OFF stateso that an excess current can be prevented from being flowed to thesubstrate 31.

While in the above-mentioned embodiment the present invention is appliedto a bipolar-type semiconductor, the capacitance of the similararrangement can be utilized in the MOS-type semiconductor.

As set forth above in detail, according to the present invention, sincethe semiconductor layer of second conductivity type is interposedbetween the semiconductor layer of first conductivity type opposing themetal layer through the dielectric layer to form the capacitor and thesemiconductor substrate, the range in which the potential is supplied tothe deriving electrode of the capacitor is extended. Also, since theinput terminal and the output terminal of the buffer to be mounted onthe semiconductor substrate are respectively connected to the metallayer and the semiconductor of the second conductivity type, thesemiconductor apparatus can be provided, in which the capacitor can beprotected from being affected by the junction capacitance between thesemiconductor layers of different conductivity types.

We claim:
 1. A semiconductor apparatus comprising a semiconductor regionof first conductivity type formed on a semiconductor substrate and asemiconductor region of second conductivity type formed in saidsemiconductor region of first conductivity type, characterized by asemiconductor capacitance having a first electrode formed on saidsemiconductor region of second conductivity type to form a capacitancethrough a dielectric layer, a second electrode connected to saidsemiconductor region of first conductivity type and a third electrodeconnected to said semiconductor region of second conductivity type, anda buffer circuit, in which at least one of said first and thirdelectrodes is connected to an input terminal of said buffer circuit, andsaid second electrode is connected to an output terminal of said buffercircuit, whereby a parasitic capacitor from said second electrode toground is substantially short-circuited by said buffer circuit.
 2. Asemiconductor apparatus according to claim 1, in which a semiconductorregion of first conductivity type is further formed on saidsemiconductor region of second conductivity type, and said semiconductorregion of said first conductivity type and said semiconductor region ofsecond conductivity type are electrically connected.
 3. A semiconductorapparatus comprising a semiconductor region of second conductivity typeformed on a semiconductor substrate consisting of a semiconductormaterial of first conductivity type, and a semiconductor region of firstconductivity type formed on said semiconductor region of secondconductivity type, characterized by a semiconductor capacitance having afirst electrode formed on said semiconductor region of firstconductivity type, a second electrode connected to said semiconductorregion of first conductivity type and a third electrode connected tosaid semiconductor region of second conductivity type, and a buffercircuit, wherein at least one of said first and second electrodes isconnected to an input terminal of said buffer circuit and said thirdelectrode is connected to an output terminal of said buffer circuit,whereby a parasitic capacitor from said second electrode to ground issubstantially short-circuited by said buffer circuit.
 4. A semiconductorapparatus according to claim 3, characterized in that a semiconductorregion of second conductivity type is further formed in saidsemiconductor region of first conductivity type, and said semiconductorregion of second conductivity type and said semiconductor region offirst conductivity type are electrically connected.